With recent improvement in integration density, performance, and operation speed of semiconductor devices, there has been a growing demand for smaller semiconductor devices. In response to this demand, various device structures have been proposed to reduce the area occupied by transistors on a substrate. Among others, field effect transistors having a fin-type structure have attracted attention as a device structure implementing a reduced occupied area. The field effect transistors having a fin-type structure are generally called fin-type field effect transistors (FETs). The fin-type field effect transistors have an active region made of a thin, wall (fin)-shaped semiconductor region (hereinafter, referred to as a fin-type semiconductor region) extending perpendicularly to a principal surface of a substrate. Since the side surfaces of the fin-type semiconductor region can be used as a channel plane, the occupied area of the transistor on the substrate can be reduced (see, e.g., PATENT DOCUMENT 1).
Examples of a method for introducing impurities into the upper and side surfaces of a fin-type semiconductor region include an ion implantation method and a plasma doping method. Recent study shows that conformal doping of the upper and side surfaces of the fin-type semiconductor region improves characteristics of fin-type FETs, and a plasma doping method has gained attention as a method of conformal doping. For example, pulsed DC (Direct Current) plasma technology has been proposed as a plasma doping method used for conformal doping (see NON-PATENT DOCUMENT 1).
FIG. 12 is a schematic perspective view showing the shapes of impurity regions right after a doping process for forming extension regions was performed in a manufacturing process of a fin-type FET in which a fin-type semiconductor region has a relatively large length in the gate width direction. In this example, the length of the fin-type semiconductor region in the gate width direction is about the same as the height of the fin-type semiconductor region (length in the gate width direction:height=1:1). As shown in FIG. 12, a gate insulating film 104 is formed so as to cover the upper surface and both side surfaces of a predetermined portion of a fin-type semiconductor region 100, and a gate electrode 105 is formed on the gate insulating film 104. Impurity regions 101, 102, and 103 are formed in a part of the fin-type semiconductor region 100 which is not covered by the gate electrode 105. The impurity region 101 is formed in the upper part of the non-covered part of the fin-type semiconductor region 100, the impurity region 102 is formed in the left side of the non-covered part of the fin-type semiconductor region 100, and the impurity region 103 is formed in the right side of the non-covered part of the fin-type semiconductor region 100. Note that the fin-type semiconductor region 100 has a length of 65 nm in the gate width direction and a height of 65 nm. The gate electrode 105 has a gate length of 38 nm.
FIG. 13 is a schematic perspective view showing the shapes of the impurity regions after the fin-type FET of FIG. 12 (which had already been subjected to the doping process) was annealed. As shown in FIG. 13, impurities in the impurity region 101 of FIG. 12 diffuse to form an impurity region 111 in the upper part of the fin-type semiconductor region 100. Impurities in the impurity region 102 of FIG. 12 diffuse to form an impurity region 112 in the left side of the fin-type semiconductor region 100, and impurities in the impurity region 103 of FIG. 12 diffuse to form an impurity region 113 in the right side of the fin-type semiconductor region 100. In this annealing process, impurities in the impurity regions 101 and 102 of FIG. 12 diffuse intensively into the upper left corner of the fin-type semiconductor region 100, and impurities in the impurity regions 101 and 103 of FIG. 12 diffuse intensively into the upper right corner of the fin-type semiconductor region 100. As a result, relatively highly doped impurity regions 114 and 115 are formed in the upper left corner and the upper right corner of the fin-type semiconductor region 100, respectively.
In the fin-type FET of FIG. 13, an ON-state current flows intensively in the upper left corner and the upper right corner of the fin-type semiconductor region 100. In other words, the fin-type FET of FIG. 13 has an uneven ON-state current, although the uneven impurity concentration in the extension regions has not been identified as a cause of this problem.
Regarding this problem, it has been reported that operation reliability of the fin-type FET is ensured by providing a curvature to the upper corners of the fin-type semiconductor region.